Unit Outline

Introduction to fundamentals of control designer concepts. Signal flow graphs will be covered with focus on cascade, parallel, controller canonical, observer canonical and phase variable forms. Frequency domain (PID) designs will be covered using a root locus to improve steady state errors and transient responses. Both cascade and feedback compensators will be considered along with the effects of both major loop and minor loop feedback configurations. Physical realisable systems for these configurations will then be shown. Time domain (state space) controllers will be used to determine pole placement strategies. Controllability and observability concepts will be introduced along with their respective transformation matrices. Feedback controllers using phase-variable, controller canonical and observer canonical forms will be discussed. State space integral controllers to improve steady state errors in time domain design will be shown. The z-transform will be discussed using basic sampling (ADC/DAC) concepts. Deriving a pulse transfer function using phantom samplers will be shown. Digital controller design concepts will be shown by mapping to the z-plane. Investigating the stability and other applications through proper selection bilinear transformation techniques. Digital controllers will be designed to meet a specified desired response using the root locus.

Intended Learning Outcomes

As per the Assessment and Results Policy 1.3, your results will reflect your achievement against specified learning outcomes.

On completion of this unit, you will be able to:


1	Analyse complex dynamic systems, and develop empirical models from process data.
2	Design advanced controllers in the time and frequency domains.
3	Implement advanced loop control strategies applied in the process industry.
4	Design, tune and troubleshoot practical implementations of industrial PID controllers.
5	Explain how relevant applied research may inform the modern practice of advanced process control engineering.

Requisites


REQUISITE TYPE	REQUISITES
Pre-requisite	ENG722

Alterations as a result of student feedback

How will I be Assessed?

For more detailed assessment information please see MyLO.

Assessment schedule


ASSESSMENT TASK #	ASSESSMENT TASK NAME	DATE DUE	WEIGHT	LINKS TO INTENDED LEARNING OUTCOMES
Assessment Task 1:	Automation report	Week 11	30 %	LO4, LO5
Assessment Task 2:	Design report	Week 12	30 %	LO1, LO2, LO3
Assessment Task 3:	Final exam	Exam Period	40 %	LO1, LO2, LO3

Assessment details

Assessment Task 1: Automation report

Task Description:

Following a laboratory exercise including programming PLCs, operating and programming industrial robots, and developing SCADA systems and interfaces, students will write a short
design report on developing an intelligent system for controlling and managing industrial plant to achieve defined automation task:
(1) Scope the automation task which can utilise PLCs, SCADA, industrial robots, and any other industrial equipment or models.
(2) Model and simulate the system.
(3) Develop controllers and supervisory and control software.
(4) Implement the designed solution using the equipment available.
(5) Evaluate the system in comparison with the modelled system.
If a pass grade is not achieved for assessment criteria 1, 3 or 4, then students will be required to resubmit and these criteria will be reassessed in order to pass ILOs 4 & 5.
GenAI use is permitted (with acknowledgement).

Task Length:

Two laboratory sessions and submission of 6 page design report.

Due Date:

Week 11

Weight:

30 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design a digital controller in PLC.	LO4
2	Interface a PLC to SCADA for control over industrial plant.	LO4
3	Design and implement a robotic interface to specifications.	LO5
4	Evaluate the performance of the system.	LO5

Assessment Task 2: Design report

Task Description:

Design project: This is a software-based design of a controller. Students will be tasked to investigate an unknown high-order plant and measure key parameters. Using their knowledge covered in class, they need to design a controller(s) to engage the plant to produce a certain desired output. The group will be posed with several unknown issues and will need to design, simulate and troubleshoot their design.
Students will be assessed through a number of complementary components including:
(1) Group final report - Written group report of 10 pages (maximum)
(2) Short summary of their individual contribution - Written individual report of 1 page (maximum)
(3) Technical group interview to discuss their design choices - Group interview of 10 minutes (maximum)
GenAI use is permitted (with acknowledgement).

Task Length:

12 page submitted design report.

Due Date:

Week 12

Weight:

30 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design a feedback compensator to mitigate the effects of unwanted dominant poles.	LO1
2	Design a low pass filter in a controller to mitigate effects of persistent oscillations.	LO3
3	Implement a cascade controller to accelerate the system's response time.	LO3
4	Design a state-space controller to meet system specification.	LO2
5	Evaluate the observer output to estimate if controller is working to specification.	LO1

Assessment Task 3: Final exam

Task Description:

In the exam the student will answer questions to demonstrate their ability to design frequency domain and time domain controllers. These designs can either manifest as continuous or discrete control implementations. GenAI is not permitted.

Task Length:

3-hour exam

Due Date:

Exam Period

Weight:

40 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design PID controllers that meet design specifications and consider trade-offs.	LO2
2	Design a state-space controller that meet design specifications and consider relevant trade-offs.	LO1, LO2
3	Design a digital controller that meet design specifications and consider the effects of sampling periods.	LO3

How your final result is determined

To pass this unit, you need to demonstrate your attainment of each of the Intended Learning Outcomes, achieve a final unit grade of 50% or greater, and pass any hurdle tasks.

Academic progress review

The results for this unit may be included in a review of your academic progress. For information about progress reviews and what they mean for all students, see Academic Progress Review in the Student Portal.

Submission of assignments

Where practicable, assignments should be submitted to an assignment submission folder in MYLO. You must submit assignments by the due date or receive a penalty (unless an extension of time has been approved by the Unit Coordinator). Students submitting any assignment in hard copy, or because of a practicum finalisation, must attach a student cover sheet and signed declaration for the submission to be accepted for marking.

Academic integrity

Academic integrity is about acting responsibly, honestly, ethically, and collegially when using, producing, and communicating information with other students and staff members.

In written work, you must correctly reference the work of others to maintain academic integrity. To find out the referencing style for this unit, see the assessment information in the MyLO site, or contact your teaching staff. For more detail about Academic Integrity, see Important Guidelines & Support.

Requests for extensions

If you are unable to submit an assessment task by the due date, you should apply for an extension.

A request for an extension should first be discussed with your Unit Coordinator or teaching support team where possible. A request for an extension must be submitted by the assessment due date, except where you can provide evidence it was not possible to do so. Typically, an application for an extension will be supported by documentary evidence: however, where it is not possible for you to provide evidence please contact your Unit Coordinator.

The Unit Coordinator must notify you of the outcome of an extension request within 3 working days of receiving the request.

Late penalties

Assignments submitted after the deadline will receive a late penalty of 5% of the original available mark for each calendar day (or part day) that the assignment is late. Late submissions will not be accepted more than 10 calendar days after the due date, or after assignments have been returned to other students on a scheduled date, whichever occurs first. Further information on Late Penalties can be found on the Assessments and Results Procedure.