Unit Outline

The unit presents a fundamental introduction to electrical circuits and is the first unit to cover this material for all engineers. It covers basic concepts used in the study of electricity and circuits, including the fundamental laws of electrical phenomena, and methods for the analysis of circuits based on the underlying physics and mathematical models. The circuit theorems are studied and applied to solve circuits containing resistors, capacitors and inductors. The unit covers transient and DC/AC circuits, including AC power analysis, three-phase circuits, frequency response and phasors. This unit is considered to be essential for all engineering students and forms the basis for many second, third and fourth year units. The unit assesses students through formal examination and the completion of a report on the practical work performed during the semester. After completing the unit, the student will be able to analyse a circuit containing single phase or three phase AC sources, as well as where transient and DC sources are present. The unit provides the student with the opportunity to become familiar with the safe operation and efficient use of electrical/electronic testing equipment.

Intended Learning Outcomes

As per the Assessment and Results Policy 1.3, your results will reflect your achievement against specified learning outcomes.

On completion of this unit, you will be able to:


1	Describe fundamental electrical and electromagnetic quantities and passive electronic components.
2	Analyse and compute the currents and potential differences in DC circuits with independent and dependent sources using mesh and nodal analysis, and equivalent circuit.
3	Analyse the transient behaviour of RC, RL and RLC circuits using linear ordinary differential equations of first and second order.
4	Analyse and optimise multi-phase multi-frequency steady state AC circuits with complex loads.

Requisites


REQUISITE TYPE	REQUISITES
Pre-requisite	KMA152 or JEE103
Anti-requisite (mutual excl)	ENG104 JEE114

Alterations as a result of student feedback

Adjustments made to ILO attainment requirements; tutorial sessions available at two different complexity levels;

How will I be Assessed?

For more detailed assessment information please see MyLO.

Assessment schedule


ASSESSMENT TASK #	ASSESSMENT TASK NAME	DATE DUE	WEIGHT	LINKS TO INTENDED LEARNING OUTCOMES
Assessment Task 1:	Semester test 1	Week 5	15 %	LO1, LO2
Assessment Task 2:	Semester test 2	Week 9	15 %	LO1, LO3
Assessment Task 3:	Fortnightly online quizzes	Refer to Assessment Description	10 %	LO1, LO2, LO3, LO4
Assessment Task 4:	Practical laboratories	Refer to Assessment Description	20 %	LO1, LO2, LO3, LO4
Assessment Task 5:	Exam	Exam Period	40 %	LO1, LO2, LO3, LO4

Assessment details

Assessment Task 1: Semester test 1

Task Description:

Part 1: DC circuits in steady state

Written invigilated closed-book test covering DC circuits in steady state.

Task Length:

90 minutes

Due Date:

Week 5

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Describe the fundamental operations of a capacitor, an inductor, and a resistor.	LO1
2	Analyse circuits containing both independent and dependent sources.	LO1
3	Apply the principles of conservation of energy and power.	LO1
4	Analyse passive components in parallel and series configurations.	LO1
5	Apply Kirchhoff's Loop & current laws.	LO1
6	Solve circuits using mesh and nodal analysis.	LO2
7	Use Thevenin and Norton equivalent circuits.	LO2
8	Solve a circuit containing a supernode.	LO2

Assessment Task 2: Semester test 2

Task Description:

Part 2: Transient response of DC circuits

Written invigilated closed-book test covering transient response of DC circuits.

Task Length:

90 minutes

Due Date:

Week 9

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Analyse independent and dependent sources.	LO1
2	Apply the principles of conservation of energy and power.	LO1
3	Analyse passive components in parallel and series configurations.	LO1
4	Apply Kirchhoff's Loop & current laws.	LO1
5	Analyse a source-free RC, RL, and RLC circuit with prescribed initial conditions.	LO3
6	Analyse the response of an RC, RL, and RLC circuit subjected to a step response input.	LO3
7	Analyse series and parallel RLC source-free circuits.	LO3

Assessment Task 3: Fortnightly online quizzes

Task Description:

After every two weeks students will complete and submit a short problem solving assignment.

Task Length:

6 x 1-hour sets of problem solving questions

Due Date:

Refer to Assessment Description

Weight:

10 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Analyse DC circuits using appropriate methods (Week 1-4).	LO1, LO2
2	Analyse multi-phase and multi-frequency circuits (Week 9-12).	LO4
3	Analyse transient responses in DC circuits (Week 5-8).	LO3

Assessment Task 4: Practical laboratories

Task Description:

Four laboratories typically contain 3 parts:

Part 1 pre-lab - mathematical analysis of provided circuit (individual).
Part 2 pre-lab - simulation of circuit behaviour (group).
Part 3 practical session - construct and measure circuit in laboratory (group).

Laboratory session 1: Induction, and building and measuring circuits and components
Duration: Week 2-3

Laboratory session 2: Basic parallel/series resistor circuit
Duration: Week 3-5

Laboratory session 3: RLC circuit with switches
Duration: Week 7-9

Laboratory session 4: AC circuits and complex loads
Duration: Week 10-12

Task Length:

4 x Laboratories consisting of 3 parts each.

Due Date:

Refer to Assessment Description

Weight:

20 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	(Lab 1-3) Explain the fundamental operations of capacitors, inductors and resistors and interpret results from circuit responses.	LO1
2	(Lab 1-3) Analyse passive components in parallel and series configurations.	LO1
3	(Lab 1) Solve circuits using mesh and nodal analysis.	LO2
4	(Lab 2) Analyse series and parallel configured source-free RC, RL, and RLC circuits with prescribed initial conditions.	LO3
5	(Lab 2) Analyse series and parallel configured RC, RL, and RLC circuits subjected to step response input.	LO3
6	(Lab 3) Analyse multi-phase and multi-frequency circuits using superposition and phasors.	LO4
7	(Lab 3) Correct the power factor for a complex load.	LO4

Assessment Task 5: Exam

Task Description:

Final open book exam.

Task Length:

3 hours

Due Date:

Exam Period

Weight:

40 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Explain the fundamental operations of capacitors, inductors and resistors and interpret results from circuit responses.	LO1
2	Analyse passive components in parallel and series configurations.	LO1
3	Solve circuits using mesh and nodal analysis.	LO2
4	Use Thevenin and Norton equivalent circuits.	LO2
5	Analyse series and parallel configured source-free RC, RL, and RLC circuits with prescribed initial conditions.	LO3
6	Analyse series and parallel configured RC, RL, and RLC circuits subjected to step response input.	LO3
7	Correct the power factor for a complex load.	LO4
8	Analyse a balanced three-phase system.	LO4
9	Analyse multi-phase and multi-frequency circuits using superposition and phasors.	LO4

How your final result is determined

To pass this unit, you need to demonstrate your attainment of each of the Intended Learning Outcomes (ILOs) and achieve a final unit grade of 50% or greater.

Specifically, to demonstrate attainment of ILOs you must achieve:

- For ILO1, an average mark of 50% or greater on all Test 1 and Test 2 questions that are clearly specified as being indicators of ILO1 attainment

- For ILO2, an average mark of 50% or greater on all Test 1 and Exam questions that are clearly specified as being indicators of ILO2 attainment

- For ILO3, an average mark of 50% or greater on all Test 2 and Exam questions that are clearly specified as being indicators of ILO3 attainment

- For ILO4, an average mark of 50% or greater on Lab 4 Assignment and Exam questions that are clearly specified as being indicators of ILO4 attainment

Academic progress review

The results for this unit may be included in a review of your academic progress. For information about progress reviews and what they mean for all students, see Academic Progress Review in the Student Portal.

Submission of assignments

Where practicable, assignments should be submitted to an assignment submission folder in MYLO. You must submit assignments by the due date or receive a penalty (unless an extension of time has been approved by the Unit Coordinator). Students submitting any assignment in hard copy, or because of a practicum finalisation, must attach a student cover sheet and signed declaration for the submission to be accepted for marking.

Academic integrity

Academic integrity is about acting responsibly, honestly, ethically, and collegially when using, producing, and communicating information with other students and staff members.

In written work, you must correctly reference the work of others to maintain academic integrity. To find out the referencing style for this unit, see the assessment information in the MyLO site, or contact your teaching staff. For more detail about Academic Integrity, see Important Guidelines & Support.

Requests for extensions

If you are unable to submit an assessment task by the due date, you should apply for an extension.

A request for an extension should first be discussed with your Unit Coordinator or teaching support team where possible. A request for an extension must be submitted by the assessment due date, except where you can provide evidence it was not possible to do so. Typically, an application for an extension will be supported by documentary evidence: however, where it is not possible for you to provide evidence please contact your Unit Coordinator.

The Unit Coordinator must notify you of the outcome of an extension request within 3 working days of receiving the request.

Late penalties

Assignments submitted after the deadline will receive a late penalty of 5% of the original available mark for each calendar day (or part day) that the assignment is late. Late submissions will not be accepted more than 10 calendar days after the due date, or after assignments have been returned to other students on a scheduled date, whichever occurs first. Further information on Late Penalties can be found on the Assessments and Results Procedure.