Unit Outline

This unit builds on the concepts and techniques of digital and analogue circuit design, and microcontroller-based development acquired in the 2nd year of the course. Topics include embedded system design utilising microcontrollers, FPGAs, DSPs and GPUs, advanced digital and analogue circuit design, PCB design and manufacture, low voltage power management design, embedded software development, digital filter and mixed signal design. In addition, students will gain an understanding of analysis and selection of architectures and systems analysis and fault finding.

Intended Learning Outcomes

As per the Assessment and Results Policy 1.3, your results will reflect your achievement against specified learning outcomes.

On completion of this unit, you will be able to:


1.	Design embedded systems using microprocessors, FPGAs, DSPs and GPUs
2.	Design power supply and management circuits for low voltage systems
3.	Write software optimised for embedded systems
4.	Resolve Electronic faults through circuit analysis

Requisites


REQUISITE TYPE	REQUISITES
Pre-requisite	ENG741 Analog Electronics ENG746 Digital Electronics KAA109 Engineering Problem Solving and Data Analysis

Alterations as a result of student feedback

How will I be Assessed?

For more detailed assessment information please see MyLO.

Assessment schedule


ASSESSMENT TASK #	ASSESSMENT TASK NAME	DATE DUE	WEIGHT	LINKS TO INTENDED LEARNING OUTCOMES
Assessment Task 1:	Power Supply Design	Week 6	15 %	LO2
Assessment Task 2:	Mechatronic system design and build with microcontroller	Week 6	15 %	LO1, LO3
Assessment Task 3:	DSP or GPU Selection	Week 10	15 %	LO1, LO4
Assessment Task 4:	Mechatronic system design and build with FPGA	Week 12	15 %	LO1, LO3, LO4
Assessment Task 5:	Exam	Exam Period	40 %	LO1, LO2, LO3, LO4

Assessment details

Assessment Task 1: Power Supply Design

Task Description:

Power Supply Design.
Students will design a power supply system and produce a report documenting the detail of their design.

Task Length:

Up to 8 pages.

Due Date:

Week 6

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design battery management circuits for low voltage systems	LO2
2	Design solar power supply circuits for low voltage systems	LO2
3	Design voltage regulation circuits for low voltage systems	LO2

Assessment Task 2: Mechatronic system design and build with microcontroller

Task Description:

Mechatronic system design and build with microcontroller.
Students will design a system and them build it in the laboratory. A report will be required to present their design and show results of the lab session.

Task Length:

2x3h in lab, 4 hours preparation, and up to 8 pages of writeup.

Due Date:

Week 6

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design digital circuits to support embedded systems.	LO1
2	Design circuit boards for low voltage systems.	LO1
3	Write C/C++ programmes for a microcontroller.	LO3
4	Write assembly language programmes for a microcontroller.	LO3

Assessment Task 3: DSP or GPU Selection

Task Description:

DSP or GPU Selection.
Students will produce a report discussing the relevant features of either a DSP or a GPU, compare at least two examples of these units and make suggestions which is a better selection according to their features and a specific application.

Task Length:

Up to 8 pages.

Due Date:

Week 10

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Explain embedded system architectures including real time operating systems with regards to their applicability to specified design scenarios.	LO1
2	Evaluate circuits’ adherence to applicable electrical/communications Australian standards and HSE	LO4

Assessment Task 4: Mechatronic system design and build with FPGA

Task Description:

Mechatronic system design and build with FPGA.
Students will design a system and them build it in the laboratory. A report will be required to present their design and show results of the lab session.

Task Length:

2x3h in lab, 4 hours preparation, and up to 8 pages of writeup.

Due Date:

Week 12

Weight:

15 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design basic digital filters to support embedded systems.	LO1
2	Design analogue circuits to support embedded systems.	LO1
3	Write code in a hardware definition language in an FPGA development environment.	LO3
4	Test electronic circuits in lab environments.	LO4
5	Write fault and test reports based on testing and analysis.	LO4

Assessment Task 5: Exam

Task Description:

Exam

Task Length:

Due Date:

Exam Period

Weight:

40 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Answer questions relating to the design of microprocessors, FPGAs, DSPs and GPUs.	LO1
2	Answer questions relating to the design of power supply circuits for low voltage systems.	LO2
3	Answer questions relating to the development of embedded system software.	LO3
4	Answer questions relating to circuit analysis and fault identification.	LO4

How your final result is determined

To pass this unit, you need to demonstrate your attainment of each of the Intended Learning Outcomes, achieve a final unit grade of 50% or greater, and pass any hurdle tasks.

Submission of assignments

Where practicable, assignments should be submitted to an assignment submission folder in MYLO. You must submit assignments by the due date or receive a penalty (unless an extension of time has been approved by the Unit Coordinator). Students submitting any assignment in hard copy, or because of a practicum finalisation, must attach a student cover sheet and signed declaration for the submission to be accepted for marking.

Requests for extensions

If you are unable to submit an assessment task by the due date, you should apply for an extension.

A request for an extension should first be discussed with your Unit Coordinator or teaching support team where possible. A request for an extension must be submitted by the assessment due date, except where you can provide evidence it was not possible to do so. Typically, an application for an extension will be supported by documentary evidence: however, where it is not possible for you to provide evidence please contact your Unit Coordinator.

The Unit Coordinator must notify you of the outcome of an extension request within 3 working days of receiving the request.

Late penalties

Assignments submitted after the deadline will receive a late penalty of 5% of the original available mark for each calendar day (or part day) that the assignment is late. Late submissions will not be accepted more than 10 calendar days after the due date, or after assignments have been returned to other students on a scheduled date, whichever occurs first. Further information on Late Penalties can be found on the Assessments and Results Procedure.

Review of results and appeals

You are entitled to ask for a review of the marking and grading of your assessment task if there is an irregularity in the marking standards or an error in the process for determining the outcome of an assessment. Details on how to request a review of a mark for an assignment are outlined in the Review and Appeal of Academic Decisions Procedure.