Unit Outline

The unit builds on knowledge of digital electronics acquired in the earlier years of the course. Students will learn how to apply the principals of digital electronics to construct complex systems such as microprocessor data paths and memory systems. These complex systems will be implemented using hardware definition language, programmed onto field programmable gate arrays (FPGA) and analysed according to logical and performance requirements.

Intended Learning Outcomes

As per the Assessment and Results Policy 1.3, your results will reflect your achievement against specified learning outcomes.

On completion of this unit, you will be able to:


1.	Analyse advanced digital systems to inform design decisions.
2.	Solve complex programming problems using assembly language.
3.	Solve problems using hardware definition language.
4.	Implement complex digital systems.
5.	Test digital systems against requirements using hardware definition language.

Requisites


REQUISITE TYPE	REQUISITES
Pre-requisite	ENG233 Digital Electronics

Alterations as a result of student feedback

How will I be Assessed?

For more detailed assessment information please see MyLO.

Assessment schedule


ASSESSMENT TASK #	ASSESSMENT TASK NAME	DATE DUE	WEIGHT	LINKS TO INTENDED LEARNING OUTCOMES
Assessment Task 1:	FPGA Laboratory	Week 7	10 %	LO3, LO4, LO5
Assessment Task 2:	Mid Semester Test	Week 7	20 %	LO1, LO3
Assessment Task 3:	MIPS Assembly Laboratory	Week 11	10 %	LO2
Assessment Task 4:	Group Project	Week 13	20 %	LO1, LO2, LO4, LO5
Assessment Task 5:	Formal Exam	Exam Period	30 %	LO1, LO2
Assessment Task 6:	Assessed Tutorials	Refer to Assessment Description	10 %	LO1, LO2, LO3, LO4, LO5

Assessment details

Assessment Task 1: FPGA Laboratory

Task Description:

Students design and implement a simple arithmetic logic unit with add and subtract capabilities using a hardware definition language. The laboratory consists of 2 x 3 hour classes. Students will be assessed on the correctness of their hardware design, the structure of their code and the execution of their design on a Field Programmable Gate Array (FPGA).

Task Length:

Written report approximately 6 to 10 pages and a 2 minute video presentation.

Due Date:

Week 7

Weight:

10 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Design a simple arithmetic logic unit using hardware definition language.	LO3
2	Prepare and execute test cases written in hardware definition language to test against requirements.	LO5
3	Implement a simple arithmetic logic unit using appropriate coding techniques with a hardware definition language.	LO4
4	Implement a hardware definitional language program on an FPGA.	LO4

Assessment Task 2: Mid Semester Test

Task Description:

Invigilated open-book test including multiple-choice and short answer questions. Topics assessed are those taught in the first half of the unit: FPGA architecture and hardware definition language programming.

Task Length:

1 hour

Due Date:

Week 7

Weight:

20 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Compare different advanced digital electronic systems to inform design decisions.	LO1
2	Explain the operation of an FPGA to inform design decisions.	LO1
3	Predict the behaviour of a hardware definition language program.	LO3
4	Identify different coding techniques with a hardware definition language.	LO3
5	Explain the structure of a hardware definition language program.	LO3

Assessment Task 3: MIPS Assembly Laboratory

Task Description:

Students will compile a number of programs from a high-level programming language into assembly language. The laboratory consists of 2 x 3 hour classes. Students will be assessed on the logical correctness, structure and adherence to conventions of their compiled assembly code. Students will also be required to explain assembly language concepts.

Task Length:

Written report of approximately 6 to 10 pages.

Due Date:

Week 11

Weight:

10 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Write assembly program that are logically the same as a high-level programming language.	LO2
2	Write assembly program that follow appropriate structural conventions.	LO2
3	Explain the properties of advanced assembly concepts including pseudo-instructions and delayed branching.	LO2

Assessment Task 4: Group Project

Task Description:

Students will work in pairs to complete a partially implemented microprocessor soft-core written in a hardware definition language. An assembly program will be developed for testing of the completed microprocessor implementation. Students will be assessed based on both the group report and an individual viva voce.

Task Length:

5 to 10 pages.

Due Date:

Week 13

Weight:

20 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Implement a complex digital circuit using hardware definition language.	LO4
2	Quantify the performance characteristics of a complex digital circuit to inform design decisions.	LO1
3	Evaluate the design to ensure it meets the requirements.	LO5
4	Write an assembly language program for testing the microprocessor.	LO2

Assessment Task 5: Formal Exam

Task Description:

Invigilated open-book examination including long and short answer questions. Topics assessed are those taught in the second half of the unit: Assembly language, microprocessor data paths and memory systems.

Task Length:

2 hours

Due Date:

Exam Period

Weight:

30 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Compare microprocessor architectures according to performance criteria.	LO1
2	Interpret complex assembly language programs.	LO2
3	Solve problems relating to microprocessor data paths and memory systems to inform design decisions.	LO1

Assessment Task 6: Assessed Tutorials

Task Description:

Tutorial activities will be assessed by the tutor in class from week 1 to week 10 inclusive. Each tutorial will be assessed as a pass or a fail based on correct completion of specified tutorial tasks. Overall mark will be determined based on the total number of passed tutorials.

Task Length:

1 hour per week from week 1 to week 10 inclusive.

Due Date:

Refer to Assessment Description

Weight:

10 %

CRITERION #

CRITERION

MEASURES INTENDED

LEARNING OUTCOME(S)


1	Identify options to modify an advanced digital system to inform the design of new functionality.	LO1
2	Write assembly language programs.	LO2
3	Write hardware definition language program to implement combinational circuits, sequential circuits and hierarchical structures.	LO3
4	Implement hardware definitional language programs on an FPGA.	LO4
5	Implement test cases for hardware definition language programs.	LO5

How your final result is determined

To pass this unit, you need to demonstrate your attainment of each of the Intended Learning Outcomes, achieve a final unit grade of 50% or greater, and pass any hurdle tasks.

Submission of assignments

Where practicable, assignments should be submitted to an assignment submission folder in MYLO. You must submit assignments by the due date or receive a penalty (unless an extension of time has been approved by the Unit Coordinator). Students submitting any assignment in hard copy, or because of a practicum finalisation, must attach a student cover sheet and signed declaration for the submission to be accepted for marking.

Requests for extensions

If you are unable to submit an assessment task by the due date, you should apply for an extension.

A request for an extension should first be discussed with your Unit Coordinator or teaching support team where possible. A request for an extension must be submitted by the assessment due date, except where you can provide evidence it was not possible to do so. Typically, an application for an extension will be supported by documentary evidence: however, where it is not possible for you to provide evidence please contact your Unit Coordinator.

The Unit Coordinator must notify you of the outcome of an extension request within 3 working days of receiving the request.

Late penalties

Assignments submitted after the deadline will receive a late penalty of 5% of the original available mark for each calendar day (or part day) that the assignment is late. Late submissions will not be accepted more than 10 calendar days after the due date, or after assignments have been returned to other students on a scheduled date, whichever occurs first. Further information on Late Penalties can be found on the Assessments and Results Procedure.

Review of results and appeals

You are entitled to ask for a review of the marking and grading of your assessment task if there is an irregularity in the marking standards or an error in the process for determining the outcome of an assessment. Details on how to request a review of a mark for an assignment are outlined in the Review and Appeal of Academic Decisions Procedure.