Unit Outline

The unit introduces the fundamental concepts of modern electronics based on semiconductor devices. On completion of this unit you will be able to design amplifier circuits with feedback. Beginning with the basic atomic structure of doped silicon substrates, diode construction, operations and characteristic curves are introduced, leading to DC and AC analysis. This is expanded to quiescent point setting and AC small-signal analysis of common transistor types (BJTs, JFETs, MOSFETs). Capacitive decoupling, voltage gain, input and output impedance, effective bandwidth, cascaded systems (both with and without the loading effect) will be explored, along with circuit component interaction on low frequency responses and parasitic effects on high frequency responses (Miller capacitance). The construction of common operational amplifiers will be reviewed and used to design active filters, with non-ideal equivalents used to describe its limitations. The benefits of an instrumentation amplifier over an operational amplifier will be investigated. Finally, the effect of shunt and series feedback on stability, gain and effective bandwidth will be analysed. These are fundamental circuit types required for control and communications systems, and advanced embedded systems, which are studied later in the degree.

Intended Learning Outcomes

As per the Assessment and Results Policy 1.3, your results will reflect your achievement against specified learning outcomes.

On completion of this unit, you will be able to:


1	Explain the characteristics and operation of low frequency (audio and below) analogue electronic circuits.
2	Design low frequency analogue electronic circuits using electronic mathematical models.
3	Construct analogue electronic circuits applicable to a communication system.
4	Analyse analogue electronics circuits with regards to their operation, characteristics and implementation.

Requisites


REQUISITE TYPE	REQUISITES
Pre-requisite	KAA112 Engineering Circuits

Alterations as a result of student feedback

None

How will I be Assessed?

For more detailed assessment information please see MyLO.

Assessment schedule


ASSESSMENT TASK #	ASSESSMENT TASK NAME	DATE DUE	WEIGHT	LINKS TO INTENDED LEARNING OUTCOMES
ASSESSMENT TASK 1:	Semester test	Week 8	15 %	LO4
ASSESSMENT TASK 2:	Practical laboratory	Week 11	20 %	LO3, LO4
ASSESSMENT TASK 3:	Design laboratory	Week 13	15 %	LO2, LO3
ASSESSMENT TASK 4:	Final Exam	Exam Period	40 %	LO1, LO2, LO4
ASSESSMENT TASK 5:	Assessed tutorial	Refer to Assessment Description	10 %	LO1, LO2, LO4

Assessment details

Assessment Task 1: Semester test

TASK DESCRIPTION:

In-semester test will be conducted to assess students’ knowledge and skills in BJT transistors and diodes.

TASK LENGTH:

90 minutes

DUE DATE:

Week 8

WEIGHT:

15 %

CRITERION #

CRITERION

MEASURES INTENDED LEARNING OUTCOME


1	Calculate the DC Q-points of BJT transistors and analyse the AC characteristics	LO4
2	Analyse DC and AC characteristics of diodes operating in various states at different instances of time.	LO4

Assessment Task 2: Practical laboratory

TASK DESCRIPTION:

Students will construct two electronic circuits per laboratory session. Each circuit's output will be measured and compared to predicted operation. The circuit is to be analysed, predictions made, and calculations provided prior to each laboratory session.

TASK LENGTH:

Two 3-hour laboratory sessions

DUE DATE:

Week 11

WEIGHT:

20 %

CRITERION #

CRITERION

MEASURES INTENDED LEARNING OUTCOME


1	Construct and measure performance of an analogue electronic circuit.	LO3
2	Compare the predicted and measure circuit performance.	LO4

Assessment Task 3: Design laboratory

TASK DESCRIPTION:

Students will design and construct a transistor circuit with specifications. Focus will be on DC, AC, and frequency analysis of the circuit. Students will provide: written proof of pre-laboratory work, a post-laboratory design report, and a post-laboratory oral presentation.

TASK LENGTH:

One 3-hour laboratory session and 5 page report

DUE DATE:

Week 13

WEIGHT:

15 %

CRITERION #

CRITERION

MEASURES INTENDED LEARNING OUTCOME


1	Design and construct a circuit to a specified performance.	LO2, LO3

Assessment Task 4: Final Exam

TASK DESCRIPTION:

Final exam

TASK LENGTH:

3 hours

DUE DATE:

Exam Period

WEIGHT:

40 %

CRITERION #

CRITERION

MEASURES INTENDED LEARNING OUTCOME


1	Solve mathematical circuit problems for a diode, transistor and operational amplifier.	LO1, LO2, LO4
2	Derive the bandwidth of transistor amplifier circuits.	LO1, LO4

Assessment Task 5: Assessed tutorial

TASK DESCRIPTION:

Students will hand in an answer to the set question, typically selected from the week’s tutorials questions. This is a weekly task, due 2 working days after each tutorial.

TASK LENGTH:

13x 1-hour tutorials (weekly)

DUE DATE:

Refer to Assessment Description

WEIGHT:

10 %

CRITERION #

CRITERION

MEASURES INTENDED LEARNING OUTCOME


1	Solve mathematical circuit problems for a diode, transistor and operational amplifier	LO1, LO2, LO4
2	Derive the bandwidth of transistor amplifier circuits	LO1, LO4

How your final result is determined

To pass this unit, you need to demonstrate your attainment of each of the Intended Learning Outcomes, achieve a final unit grade of 50% or greater, and pass any hurdle tasks.

Submission of assignments

Where practicable, assignments should be submitted to an assignment submission folder in MYLO. You must submit assignments by the due date or receive a penalty (unless an extension of time has been approved by the Unit Coordinator). Students submitting any assignment in hard copy, or because of a practicum finalisation, must attach a student cover sheet and signed declaration for the submission to be accepted for marking.

Requests for extensions

If you are unable to submit an assessment task by the due date, you should apply for an extension.

A request for an extension should first be discussed with your Unit Coordinator or teaching support team where possible. A request for an extension must be submitted by the assessment due date, except where you can provide evidence it was not possible to do so. Typically, an application for an extension will be supported by documentary evidence: however, where it is not possible for you to provide evidence please contact your Unit Coordinator.

The Unit Coordinator must notify you of the outcome of an extension request within 3 working days of receiving the request.

Late Penalties

Assignments submitted after the deadline will receive a late penalty of 5% of the original available mark for each calendar day (or part day) that the assignment is late. Late submissions will not be accepted more than 10 calendar days after the due date, or after assignments have been returned to other students on a scheduled date, whichever occurs first. Further information on Late Penalties can be found on the Assessments and Results Procedure.

Review of results and appeals

You are entitled to ask for a review of the marking and grading of your assessment task if there is an irregularity in the marking standards or an error in the process for determining the outcome of an assessment. Details on how to request a review of a mark for an assignment are outlined in the Review and Appeal of Academic Decisions Procedure.